GD25B127DPFS datasheet(16/65 Pages) GIGADEVICE

tên linh kiện	GD25B127DPFS

Giải thích chi tiết về linh kiện	3.3V Uniform Sector Dual and Quad Serial Flash

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16 / 65 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B127D

7.1.

Write Enable (WREN) (06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)

bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status

goes low  sending the Write Enable command  CS# goes high.

Figure3. Write Enable Sequence Diagram

7.2. Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:

CS# goes lowSending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-

up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase,

Erase/Program Security Registers and Reset commands.

Figure4. Write Disable Sequence Diagram

Command

06H

CS#

SCLK

High-Z

Command

04H

CS#

SCLK

High-Z

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