PI7C7100 datasheet(39/132 Pages) PERICOM

39 / 132 page

09/18/00 Rev 1.1

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

32-bit value of 0 is compared to the prefetchable memory base address upper 32 bits register and the prefetchablememory

limit address upper 32 bits register. The prefetchable memory base address upper 32 bits register must be 0 to pass any single

address cycle transactions downstream.

Prefetchable memory address range has a granularity and alignment of1MB.Maximummemoryaddressrangeis 4GB when

32-bit addressing is being used.

Prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration

offset 24h and by a 16-bit prefetchable memory limit address register at offset 26h. The top 12 bits of each of these registers

correspond to bits [31:20] of the memory address. The lowest 4 bits are hardwired to 1h. The lowest 20 bits of the

prefetchable memory base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary.

The lowest 20 bits of the prefetchable memory limit address are assumed to be FFFFFh, which results in an alignment to

the top of a 1MB block.

Note: The initial state of the prefetchable memory base address register is 0000 0000h. The initial state of the prefetchable

memory limit address register is 000F FFFFh. Note that the initial states of these registers define a prefetchable memory

range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the

memory enable bit or the master enable bit in the command register in configuration space.

To turn off the prefetchable memory address range, write the prefetchable memory base address register with a value

greater than that of the prefetchable memory limit address register. The entire base value must be greater than the entire

limit value, meaning that the upper 32 bits must be considered. Therefore, to disable the address range, the upper 32

bits registers can both be set to the same value, while the lower base register is set greater than the lower limit register.

Otherwise, the upper 32-bit base must be greater than the upper 32-bit limit.

5.4 VGA Support

PI7C7100 provides two modes for VGA support:

• VGA mode, supporting VGA-compatible addressing

• VGA snoop mode, supporting VGA palette forwarding

5.4.1 VGA Mode

When a VGA-compatible device exists downstream from PI7C7100, set the VGA mode bit in the bridge control register

in configuration space to enable VGA mode. When PI7C7100 is operating in VGA mode, it forwards downstream those

transactions addressing the VGA frame buffer memory and VGA I/O registers, regardless of the values of the base and

limit address registers. PI7C7100 ignores transactions initiated on the secondary interface addressing these locations.

The VGA frame buffer consists of the following memory address range:

000A 0000h–000B FFFFh

Read transactions to frame buffer memory are treated as non-prefetchable. PI7C7100 requests only a single data transfer

from the target, and read byte enable bits are forwarded to the target bus.

The VGA I/O addresses are in the range of 3B0h–3BBh and 3C0h–3DFh I/O. These I/O addresses are aliases every 1KB

throughout the first 64KB of I/O space. This means that address bits <15:10> are not decoded and can be any value, while

address bits [31:16] must be all 0s. VGA BIOS addresses starting at C0000h are not decoded in VGA mode.

5.4.2 VGA Snoop Mode

PI7C7100 provides VGA snoop mode, allowing for VGA palette write transactions to be forwarded downstream. This mode

is used when a graphics device downstream from PI7C7100 needs to snoop or respond to VGA palette write transactions.

To enable the mode, set the VGA snoop bit in the command register in configuration space. Note that PI7C7100 claims

VGA palette write transactions by asserting DEVSEL# in VGA snoop mode.

When VGA snoop bit is set, PI7C7100 forwards downstream transactions within the 3C6h, 3C8h and 3C9h I/O addresses

space. Note that these addresses are also forwarded as part of the VGA compatibility mode previously described. Again,

address bits <15:10> are not decoded, while address bits <31:16> must be equal to 0, which means that these addresses

are aliases every 1KB throughout the first 64KB of I/O space.

Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C7100 behaves in the same way as if only the VGA

mode bit were set.

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