LAN91C96ITQFP datasheet(21/110 Pages) SMSC

21 / 110 page

Non-PCI Single-Chip Full Duplex Ethernet Controller

SMSC DS – LAN91C96I

Page 21

Rev. 11/18/2004

DATASHEET

If the system to SRAM bandwidth is insufficient the LAN91C96I will automatically use its IOCHRDY line for

flow control. However, for Local Bus, IOCHRDY will never be negated.

The LAN91C96I consists of an integrated Ethernet controller mapped entirely in I/O space.

The Ethernet controller function includes a built-in 6kbyte RAM for packet storage. This RAM buffer is

accessed by the CPU through sequential access regions of 256 bytes each. The RAM access is internally

arbitrated by the LAN91C96I, and dynamically allocated between transmit and receive packets. Each packet

may consist of one or more 256 byte page. The Ethernet controller functionality is identical to the LAN91C94

and LAN91C95 except where indicated otherwise.

The LAN91C96I Memory Management Unit parameters are:

RAM size

6kbytes

Max. number of pages

Max. number of

packets

24 (FIFOs have 24

entries of 5 bits)

Max. pages per packet

Page Size

256 bytes

5.1

Buffer Memory

The logical addresses for RAM access are divided into TX area and RX area.

The TX area is seen by the CPU as a window through which packets can be loaded into memory before

queuing them in the TX FIFO of packets. The TX area can also be used to examine the transmit

completion status after packet transmission.

The RX area is associated to the output of the RX FIFO of packets, and is used to access receive packet

data and status information.

The logical address is specified by loading the address pointer register. The pointer can automatically

increment on accesses.

All accesses to the RAM are done via I/O space.

A bit in the address pointer also specifies if the address refers to the TX or RX area.

In the TX area, the host CPU has access to the next transmit packet being prepared for transmission. In

the RX area, it has access to the first receive packet not processed by the CPU yet.

The FIFO of packets, existing beneath the TX and RX areas, is managed by the MMU. The MMU

dynamically allocates and releases memory to be used by the transmit and receive functions.

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