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SC4810EITMLRT bảng dữ liệu(PDF) 14 Page - Semtech Corporation |
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SC4810EITMLRT bảng dữ liệu(HTML) 14 Page - Semtech Corporation |
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14 / 24 page ![]() 14 2004 Semtech Corp. www.semtech.com SC4810A/B/C/D/E POWER MANAGEMENT Application Information (Cont.) FB GND R1 VREF R2 Vout VBias R3 R4 R5 SC431 Fig.9 Cycle-by-cycle over-current limitation ) 3 ........( V 3 . 1 V 2 V CS FB + • = ) 4 ........( R R R V V 2 1 2 REF FB + • = Synchronization SC4810 features a special synchronization function which is leading-edge triggered with a threshold set to 2.1V. Applications like multi-phase interleaving can be achieved using the SYNC pin. When the SYNC pin is con- nected to the RCT pin of the master SC4810, the out- puts of the two SC4810’s will be out of phase. The fre- quency of the master SC4810 clock signal should be at least 30% faster than that of the slave SC4810 for the guaranteed synchronization. SYNC pin should be grounded if synchronization is unused. (The patent for the synchronization scheme is pending). The synchronous function is illustrated as in Fig. 10. VRCT t 3V 0V Clock Signal of the Master SC4810 0V 2.1V 0V t t OUT1 of the Master SC4810 OUT1 of the Slave SC4810 Fig. 10 Illustration for Synchronization |
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