GPR25L3203F datasheet(21/47 Pages) GENERALPLUS

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GPR25L3203F

Proprietary & Confidential

Jul. 09, 2015

Version: 1.0

10.16.Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the

chosen sector to be "1". The instruction is used for any 4K-byte

sector. A Write Enable (WREN) instruction must execute to set the

Write Enable Latch (WEL) bit before sending the Sector Erase

(SE). Any address of the sector (see "Table 3. Memory

Organization" ) is a valid address for Sector Erase (SE) instruction.

The CS# must go high exactly at the byte boundary (the least

significant bit of the address has been latched-in); otherwise, the

instruction will be rejected and not executed.

The sequence of issuing SE instruction is: CS# goes low →

sending SE instruction code→ 3-byte address on SI →CS# goes

high.

The SIO[3:1] are don't care.

The self-timed Sector Erase Cycle time (tSE) is initiated as soon

as Chip Select (CS#) goes high. The Write in Progress (WIP) bit

still can be checked while the Sector Erase cycle is in progress.

The WIP sets during the tSE timing, and clears when Sector Erase

Cycle is completed, and the Write Enable Latch (WEL) bit is

cleared. If the sector is protected by BP3~0, the array data will be

protected (no change) and the WEL bit still be reset.

Figure 19. Sector Erase (SE) Sequence (Command 20)

10.17.Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the

chosen block to be "1". The instruction is used for 64K-byte block

erase operation. A Write Enable (WREN) instruction must be

executed to set the Write Enable Latch (WEL) bit before sending

the Block Erase (BE). Any address of the block (see "Table 3.

Memory Organization") is a valid address for Block Erase (BE)

instruction. The CS# must go high exactly at the byte boundary

(the least significant bit of address byte has been latched-in);

otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE instruction is: CS# goes low →

sending BE instruction code → 3-byte address on SI → CS# goes

high.

The SIO[3:1] are don't care.

The self-timed Block Erase Cycle time (tBE) is initiated as soon as

Chip Select (CS#) goes high. The Write in Progress (WIP) bit still

can be checked while the Sector Erase cycle is in progress. The

WIP sets during the tBE timing, and clears when Sector Erase

Cycle is completed, and the Write Enable Latch (WEL) bit is

cleared. If the block is protected by BP3~0, the array data will be

protected (no change) and the WEL bit still be reset.

Figure 20. Block Erase (BE) Sequence (Command D8)

10.18.Block Erase (BE32K)

The Block Erase (BE32K) instruction is for erasing the data of the

chosen block to be "1". The instruction is used for 32K-byte block

erase operation. A Write Enable (WREN) instruction must be

executed to set the Write Enable Latch (WEL) bit before sending

the Block Erase (BE32K). Any address of the block (see "Table 3.

Memory Organization" ) is a valid address for Block Erase (BE32K)

instruction. The CS# must go high exactly at the byte boundary

(the least significant bit of address byte has been latched-in);

otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE32K instruction is: CS# goes low →

sending BE32K instruction code → 3-byte address on SI → CS#

goes high.

The SIO[3:1] are don't care.

The self-timed Block Erase Cycle time (tBE32K) is initiated as

soon as Chip Select (CS#) goes high. The Write in Progress (WIP)

bit still can be checked while the Sector Erase cycle is in progress.

The WIP sets during the tBE32K timing, and clears 0 when Sector

Erase Cycle is completed, and the Write Enable Latch (WEL) bit is

cleared. If the block is protected by BP3~0, the array data will be

protected (no change) and the WEL bit still be reset.

Figure 21. Block Erase 32KB (BE32K) Sequence (Command 52)

10.19.Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the

whole chip to be "1". A Write Enable (WREN) instruction must be

executed to set the Write Enable Latch (WEL) bit before sending

the Chip Erase (CE). The CS# must go high exactly at the byte

boundary; otherwise, the instruction will be rejected and not

executed.

The sequence of issuing CE instruction is: CS# goes low →

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