ADC0803, ADC0805

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH DIFFERENTIAL INPUTS

SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986

6

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

The ADC0803 and ADC0805 each contain a circuit equivalent to 256-resistor network. Analog switches are

corresponding tap on the 256R network. The most significant bit (MSB) is tested first. After eight spelled out

comparisons (64 clock periods), an eight-bit binary code (1111 1111 = full scale) is transferred to an output latch and

the interrupt (INTR) output goes low. The device can be operated in a free-running mode by connecting the INTR

output to the write (WR) input and holding the conversion start (CS) input at a low level. To ensure start up under all

conditions, a low-level WR input is required during the power-up cycle. Taking CS low any time after that will interrupt

a conversion in process.

When WR goes low, the internal successive-approximation register (SAR) and 8-bit shift register are reset. As long

as both CS and WR remain low, the analog-to-digital converter remains in a reset state. One to eight clock periods

after CS or WR makes a low-to-high transition, conversion starts.

When CS and WR are low, the start flip-flop is set and the interrupt flip-flop and 8-bit register are reset. The next clock

pulse transfers a logic high to the output of the start flip-flop. The logic high is ANDed with the next clock pulse, placing

a logic high on the reset input of the start flip-flop. If either CS or WR have gone high, the set signal to the start flip-flop

is removed, causing it to be reset. A logic high is placed on the D input of the eight-bit shift register and the conversion

process is started. If CS and WR are still low, the start flip-flop, the 8-bit shift register, and the SAR remain reset.

This action allows for wide CS and WR inputs, with conversion starting from one to eight clock periods after one of

the inputs goes high.

When the logic high input has been clocked through the 8-bit shift register, which completes the SAR search, it is

applied to an AND gate controlling the output latches and to the D input of a flip-flop. On the next clock pulse, the digital

word is transferred to the 3-state output latches and the interrupt flip-flop is set. The output of the interrupt flip-flop

is inverted to provide an INTR output that is high during conversion and low when the conversion is complete.

When a low is at both CS and RD, an output is applied to the DB0 through DB7 outputs and the interrupt flip-flop is

reset. When either CS or RD return to a high state, the DB0 through DB7 outputs are disabled (returned to the

high-impedance state). The interrupt flip-flop remains reset.