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AW3643CSR bảng dữ liệu(PDF) 21 Page - Shanghai awinic technology co.,ltd

tên linh kiện AW3643CSR
Giải thích chi tiết về linh kiện  High Efficiency, Dual 1.5A Flash LED Driver
PDF  39 Pages
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nhà sản xuất  AWINIC [Shanghai awinic technology co.,ltd]
Trang chủ  http://www.awinic.com.cn/index.php
Logo AWINIC - Shanghai awinic technology co.,ltd

AW3643CSR bảng dữ liệu(HTML) 21 Page - Shanghai awinic technology co.,ltd

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AW3643
Jan 2018 V1.4
www.awinic.com.cn
21
Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
Flash Event
VIN
VIN
VIN
Flash Current
Flash Current
Flash Current
Hysteresis = 0 or 50mV
Target Flash Current
IVFM-Threshold
IVFM-Threshold
IVFM-Threshold
Flash Current with
IVFM Disable
Stop & Hold
Mode
Down
Mode
Up & Down
Mode
Hysteresis = 0 or 50mV
Fig 50
IVFM Modes
FLASH TIMEOUT
The Flash Timeout period sets the maximum time of one flash event, whether a flash stop command is
received or not. The AW3643 has 16 timeout levels ranging from 40ms to 1.6s (see TIMING
CONFIGURATION REGISTER (0X08) for more detail). Flash Timeout applies to both Flash and IR modes,
and it continues to count when the Flash mode is forced into Torch mode during a TX high event. The mode
bits are cleared and bit[0] is set in the Flags1 register(0x0A) upon a Flash Timeout. This fault flag can be reset
to '0' by reading back the Flags1 Register (0x0A), or by setting HWEN to '0', or by setting the SW RESET bit
to a '1', or by removing power to the AW3643.
CURRENT LIMIT
When the inductor current limit is reached, the AW3643 terminates the charging phase of the switching cycle
until the next switching period. If the over-current condition persists, the device operates continuously in
current limit. The AW3643 features two selectable inductor current limits(1.9A and 2.8A) that are
programmable by bit[0] in Boost configuration Register(0x07).
Since the current limit is sensed in the NMOS switch, there is no mechanism to limit the current when the
device operates in Pass Mode (current does not flow through the NMOS in pass mode). The mode bits are
not cleared upon a Current Limit event, but a flag bit[3] is set in the Flags1 register(0x0A).



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