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MSELP bảng dữ liệu(PDF) 3 Page - Mixed Signal Integration |
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MSELP bảng dữ liệu(HTML) 3 Page - Mixed Signal Integration |
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3 / 7 page ![]() Switched Capacitor Elliptic Lowpass Filter Data Sheet 4/2004 Pin Configuration 1 2 3 4 5 6 7 14 13 12 11 10 9 8 INV2 INV1 R VSS CLK FIN NINV OUT2 FOUT OUT1 GND VDD FO PS Web Site “www.mix-sig.com” © 2004 Mixed Signal Integration 3 1 NINV Second Op Amp Non Inverting Input 2 OUT2 Second Op Amp Output 3 FOUT Filter Output 4 OUT1 First Op Amp Output 5 GND Ground Pin, 0V for Split Supplies Typically 2.5V for Single Supply 6 VDD Positive Power Supply, Typically 2.5V for Split Supplies, 5V for Single Supply 7 PS Power Select Pin (See Electrical Characteristics) 8 FIN Filter Input 9 CLK Clock Input 10 VSS Negative Power Supply, Typically -2.5V for Split Supplies, 0V for Single Supply 11 R Connection for the Clock Resistor (NC when using external clock) 12 FO Clock to Corner Select Pin, CMOS level 13 INV1 First Op Amp Inverting Input 14 INV2 Second Op Amp Inverting Input Pin Description 1 NINV Second Op Amp Non Inverting Input 2 OUT2 Second Op Amp Output 3 FOUT Filter Output 4 OUT1 First Op Amp Output 5 GND Ground Pin, 0V for Split Supplies Typically 2.5V for Single Supply 6 VDD Positive Power Supply, Typically 2.5V for Split Supplies, 5V for Single Supply 7 PS Power Select Pin (See Electrical Characteristics) 8 NC No Connection 9 NC No Connection 10 VSS Negative Power Supply, Typically -2.5V for Split Supplies, 0V for Single Supply 11 12 13 R Connection for the Clock Resistor (NC when using external clock) 14 FO Clock to Corner Select Pin, CMOS level 15 INV1 First Op Amp Inverting Input 16 INV2 Second Op Amp Inverting Input |
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