PSD813F1 datasheet(72/110 Pages) STMICROELECTRONICS

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PSD813F1

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JTAG Extensions

TSTAT and TERR are two JTAG extension signals

enabled by an “ISC_ENABLE” command received

over the four standard JTAG pins (TMS, TCK, TDI,

and TDO). They are used to speed programming

and erase functions by indicating status on PSD

pins instead of having to scan the status out seri-

ally using the standard JTAG channel.

TERR will indicate if an error has occurred when

erasing a sector or programming a byte in Flash

memory. This signal will go Low (active) when an

error condition occurs, and stay Low until an

“ISC_CLEAR” command is executed or a chip re-

set pulse is received after an “ISC-DISABLE” com-

mand. TERR does not apply to EEPROM.

TSTAT behaves the same as the Ready/Busy sig-

nal described in the section entitled Ready/Busy

Pin (PC3), page 18. TSTAT will be High when the

PSD device is in READ mode (Flash memory and

EEPROM contents can be read). TSTAT will be

Low when Flash memory programming or erase

cycles are in progress, and also when data is be-

ing written to EEPROM.

TSTAT and TERR can be configured as open-

drain type signals during an “ISC_ENABLE” com-

mand. This facilitates a wired-OR connection of

TSTAT signals from several PSD devices and a

wired-OR connection of TERR signals from those

same devices. This is useful when several PSD

devices are “chained” together in a JTAG environ-

ment.

Security, Flash memory and EEPROM

Protection

When the security bit is set, the device cannot be

read on a device programmer or through the JTAG

Port. When using the JTAG Port, only a full chip

erase command is allowed. All other program/

erase/verify commands are blocked. Full chip

erase returns the part to a non-secured blank

state. The Security Bit can be set in PSDsoft Ex-

press Configuration.

All Flash Memory and EEPROM sectors can indi-

vidually be sector protected against erasures. The

sector protect bits can be set in PSDsoft Express

Configuration.

Table 34. JTAG Port Signals

INITIAL DELIVERY STATE

When delivered from ST, the PSD device has all

bits in the memory and PLDs set to '1.' The PSD

Configuration Register bits are set to '0.' The code,

configuration, and PLD logic are loaded using the

programming procedure. Information for program-

ming the device is available directly from ST.

Please contact your local sales representative.

Table 35. JTAG Enable Register

Note: The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Configura-

tion bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is used

to enable the JTAG signals.

Port C Pin

JTAG Signals

Description

PC0

TMS

Mode Select

PC1

TCK

Clock

PC3

TSTAT

Status

PC4

TERR

Error Flag

PC5

TDI

Serial Data In

PC6

TDO

Serial Data Out

Bit 0

JTAG_Enable

0 = off JTAG port is disabled.

1 = on JTAG port is enabled.

Bit 1