ComLink™ Series
CY2DP818
Document #: 38-07061 Rev. *A
Page 2 of 8
Maximum Ratings[1]
Storage Temperature: ................................–65
°C to + 150°C
Ambient Temperature:................................... –40
°C to +85°C
Supply Voltage to Ground Potential
(Inputs and VCC only)....................................... –0.3V to 4.6V
Supply Voltage to Ground Potential
(Outputs only) ........................................ –0.3V to VDD + 0.3V
DC Input Voltage ................................... –0.3V to VDD + 0.3V
DC Output Voltage................................. –0.3V to VDD + 0.9V
Power Dissipation........................................................ 0.75W
Notes:
1.
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Pin Description
Pin Number
Pin Name
Pin Standard Interface
Description
1, 9,12,18,19,20,38
GND
POWER
Ground
2,3,4,5,6,8, 13,14,15,16,17,29
VDD
POWER
Power Supply
10,11
Input A, Input B
Default: LVPECL/LDVS
Optional: LVTTL/LVCMOS
single pin
Differential input pair or single line.
LVPECL/LVDS default. See InConfig,
below.
37, 36,35,34,
33,32,31, 30,
28,27,26,25,
24,23,22,21
Q1(A,B), Q2(A,B)
Q3(A,B), Q4(A,B)
Q5(A,B), Q6(A,B)
Q7(A,B), Q8(A,B)
LVPECL
Differential Outputs
7
InConfig
LVTTL/LVCMOS
Converts inputs from the default
LVPECL/LVDS
(logic = 0)
To
LVTTL/LVCMOS
(logic = 1)
See Figure 4 and Figure 5 for additional
Information
Table 1. Power Supply Characteristics
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
ICCD
Dynamic Power Supply Current
VDD = Max.
Input toggling 50% Duty Cycle,
Outputs Open
1.5
2.0
mA/MHz
IC
Total Power Supply Current
VDD = Max.
Input toggling 50% Duty Cycle,
Outputs 50 ohms
fL=100 MHz
350
mA
IC Core
Core current when output loads are
disabled
VDD = Max.
Input toggling 50% Duty Cycle, Outputs
Disabled, not connected to VTT
fL=100 MHz
50
mA
Table 2. Input Receiver Configuration for Differential or LVTTL/LVCMOS
INCONFIG
Pin 7
Binary Value
Input Receiver Family
Input Receiver Type
1
LVTTL in LVCMOS
Single-ended, non-inverting, inverting, void of bias resistors
0
LVDS
Low-voltage differential signaling
LVPECL
Low-voltage pseudo (positive) emitter coupled logic
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