GPF8F Series

© Generalplus Technology Inc.

Proprietary & Confidential

6

Aug. 03, 2018

Version: 1.1

6 SIGNAL DESCRIPTIONS

Mnemonic

Type

Description

PORT A, Port B

IOA [15:0]

I/O

IOA[15:0]: bi-direction I/O ports

It is programmable as wakeup I/O pins.

IOB [15:0]

I/O

IOB [15:0]: bi-directional I/O ports.

It is programmable as wakeup I/O pins.

Power & GND

VDD_IOA1

P

Power for IOA0~IOA9

VSS_IOA1

G

Ground for IOA0~IOA9

VDD_IOA2

P

Power for IOA10~IOA15

VSS_IOA2

G

Ground for IOA10~IOA15

VDD_IOB1

P

Power for IOB---5V domain

VDD_IOB2

P

Power for IOB---5V domain

VSS_IOB

G

Ground for IOB

V33ADC_REGO

P

3.3V Power output from regulator for CODEC ADC (3.3V)

VSS_ADC

G

Ground for CODEC ADC

V33_REGO

P

3.3V Power output from regulator

V18_REGO

P

1.8V Power output from regulator, for core power

VDD_REGIN

P

Power supply for regulator (2.2V~5.5V)

VSS_REG

G

Ground reference for regulator

VDD_DAC

P

Positive 5V supply for push-pull DAC

VSS_DAC

G

Ground reference for push-pull DAC

VDD_PDAC

P

Positive 5V supply for push-pull DAC post driver

VSS_PDAC

G

Ground reference for push-pull DAC post driver

OPTION

TEST

I

TEST Mode selection pin, high is test mode and low is normal mode (Pad internal pull

low)

—3V domain

DAC

AUDP

O

Audio output of push pull DAC

AUDN

O

Audio output of push pull DAC

ACIN

U

Audio analog mixer in

ADC

MICIN

I

Microphone input

—3V domain, pad power from V333ADC_REGO

ADVCM

I

Common

voltage(1/2*VDD)

for

amplifier

and

ADC

—3V domain, pad power from

V333ADC_REGO

ICE

ICE_CLK

I

ICE clock (with pull low)

—3V domain, pad power from V33_REGO

ICE_SDA

I/O

ICE serial data bus

—3V domain, pad power from V33_REGO

ICE_EN

I

ICE enable (high active , with pull low)

—3V domain, pad power from V33_REGO

Other Signal

RESETB

I

System reset pin (active low) (internal 47Kohm pull high resistor) , pad power from

VDD_IOB1 / VDD_IOB2