GPC71PXXXA

© Generalplus Technology Inc.

Proprietary & Confidential

13

Dec. 20, 2016

Version: 1.2

9.2 Heavy Loading or Circuit with Noise

VDD

PVDD

PVSS

AUDP

IOA[3:0]

AUDN

IOA[3:0]

IOB[3:0]

IOB[3:0]

IOC[3:0]

IOC[3:0]

IOD[3:0]

IOD[3:0]

PVDD

PVSS

VDDIO

VSS

VSS1

REGOUT

VSS2

VSS

Battery

PVDD

PVSS

0.1u

C1

10

C2

47u

VDD

0.1u

C3

VPP

VPP

R1

VSS

0.1u~2.2u

C3

VDDTRM

NC

TEST

NC

PCB Layout Guidelines:

1. PVDD may be greater than or equal to VDD.

2. VSS, PVSS must be connected to ground input directly, not the branch of each other.

3. A typical value of C1 is 47uf, and it should vary in different loadings.

4. If there is application with motor, REGOUT should be connected with C3.

5. IOC/IOD isn

’t supported in GPC71P032A/GPC71P016A.

6. There is no

“TEST” pin in GPC71P032A/GPC71P016A.