GPC3XXXAx/Bx/Cx/Dx

© Generalplus Technology Inc.

Proprietary & Confidential

28

Aug. 28, 2017

Version: 2.3

9.3. Application Circuit with Low Loading for GPC3341A

GPC3341A

IOA[7:0]

IOA[7:0]

IOB[7:0]

IOB[7:0]

IOC[7:0]

IOC[7:0]

RESB

VSS

0.1u - 4.7uF

C1*

VSS

Battery

VDDIO

PVDD

VDD_REGIN

VSSIO

PVSS

AUDP

AUDN

PVDD

VDDIO

VDD_REGIN

PVSS

VSSIO

CVSS

VSSIO

VSS

VDDIO

VDD_REGIN

PVDD

PVSS

VDD_REGOUT

2.2u

VSS

C5

PCB Layout Guidelines:

1. VDD_REGIN, VDDIO and PVDD should be connected to power input port directly rather than the branch of each other.

2. VDD_REGIN should be equal to VDDIO.

3. PVDD should be greater than or equal to VDD_REGIN and VDDIO.

4. CVSS, VSSIO and PVSS should be connected to ground input directly rather than the branch of each other.

5. When using two batteries, C1 should be 0.1uF~4.7uF and should be increased for a high-volume application.