MSM82C54-2JS datasheet(7/23 Pages) OKI

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¡ Semiconductor

MSM82C54-2RS/GS/JS

DESCRIPTION OF PIN FUNCTIONS

16 bits

Adress Bus

Control Bus

D7 - 0

A1 A0

8 bits

Data Bus

MSM82C54-2

OUT GATE CLK

Counter #0

OUT GATE CLK

Counter #1

OUT GATE CLK

Counter #2

SYSTEM INTERFACING

D7 - D0

Name

Bidirectional

Data Bus

Input/Output

Pin Symbol

Input/Output

Function

Read Input

Input

Write Input

Input

A0, A1

Address Input

Input

CLK0 - 2

Clock Input

Input

GATE0 - 2

Gate Input

Input

Three-state 8-bit bidirectional data bus used when writing control

words and count value, and reading count values upon reception of

WR and RD signals from CPU.

Chip Select

Input

Data transfer with the CPU is enabled when this pin is at low level.

When at high level, the data bus (D0 thru D7) is switched to high

impedance state where neither writing nor reading can be executed.

Internal registers, however, remain unchanged.

Data can be transferred from MSM82C54-2 to CPU when this pin is

at low level.

Data can be transferred from CPU to MSM82C54-2 when this pin is

at low level.

One of the three internal counters or the control word register is

selected by A0/A1 combination. These two pins are normally

connected to the two lower order bits of the address bus.

Supply of three clock signals to the three counters incorporated in

MSM82C54-2.

Control of starting, interruption, and restarting of counting in the

three respective counters in accordance with the set control word

contents.

OUT0 - 2

Counter Output

Output

Output of counter output wave form in accordance with the set

mode and count value.

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