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¡ Semiconductor

MSM80C85AHRS/GS/JS

BASIC SYSTEM TIMING

The MSM80C85AH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower

8-bits of address on the Data Bus. Figure 5 shows an instruction fetch, memory read and I/O

write cycle (as would occur during processing of the OUT instruction). Note that during the I/

O write and read cycle that the I/O port address is copied on both the upper and lower half of

the address.

There are seven possible types of machine cycles. Which of these seven takes place is defined

INTA). (See Table 2.) The status line can be used as advanced controls (for device selection, for

lines RD and WR become active later, at the time when the transfer of data is to take place, so

are used as command lines.

A machine cycle normally consists of three T states, with the exception of OPCODE FETCH,

which normally has either four or six T states (unless WAIT or HOLD states are forced by the

receipt of READY or HOLD inputs). Any T state must be one of ten possible states, shown in

Table 3.

Memory Read

O

O

Memory Write

I/O Read

1

1

I/O Write

(MR)

Opcode Fetch

0

(OF)

(MW)

(IOR)

Acknowledge of INTR

1

(INA)

(IOW)

Bus Idle

0

1

TS

1

0

1

0

1

1

1

1

0

O

1

O

1

1

1

0

1

0

O

1

O

1

0

1

1

1

TS

1

0

1

0

1

1

1

1

TS

1

1

1

1

1

IO/

M

RD

WR

INTA

Machine Cycle

Status

Control

0

1

1

1

(BI): DAD

ACK. OF

RST, TRAP

HALT

Table 2 MSM80C85AH Machine Cycle Chart