5402AS–BDC–11/04

Features

Ω Terminated)

– Only Rising: CLK and DR Mode

– Rising and Falling: CLK/2 and DR/2 Mode

– Compensation of External Data and Clock Path Misalignment and Skews

– Once Tuned, Setting is Valid over Full Operating Frequency and Over Full

Specified Temperature Range

Screening

–-40

° C < T

Applications

This DMUX enables users to process high-speed output data streams from fast ana-

log-to-digital converters down to standard FPGA processor speed.

Description

The AT84CS001 is a monolithic high-speed demultiplexer, used to lower a 10-bit data

stream of up to 2.2 Gsps guaranteed rate by a selectable 4 or 2 ratio (a 1:8 ratio may

be achieved by interleaving two DMUXes).

The DMUX is a companion chip designed to fit perfectly with all of Atmel’s high-speed

ADCs and is capable of tracking the ADC’s output sampling rate over all operating fre-

quency and temperature ranges.

Thanks to its LVDS buffers, this DMUX can easily be interfaced with standard high-

speed FPGAs (100

Ω differentially terminated).

The AT84CS001 has the same footprint as Atmel’s TS81102G0 DMUX, with a very

similar pinout. Minimum re-design efforts are required to use this low-power DMUX.

An application note “Replacing Atmel’s TS81102G0 DMUX with Atmel’s AT84CS001

LVDS DMUX” reference 5413, is available to assist in migrating from the TS81102G0

to the AT84CS001.

10-bit 1:2/4

2.2 GHz LVDS

DMUX

AT84CS001

Summary

This is a summary document. A complete document is not

available at this time. For more information, please contact

your local Atmel sales office.