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PIC12F635E/P bảng dữ liệu(PDF) 65 Page - Microchip Technology |
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PIC12F635E/P bảng dữ liệu(HTML) 65 Page - Microchip Technology |
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65 / 196 page ![]() © 2005 Microchip Technology Inc. Preliminary DS41232B-page 63 PIC12F635/PIC16F636/639 7.3 Comparator Configuration There are eight modes of operation for the comparators. The CMCON0 register is used to select these modes. Figure 7-3 and Figure 7-4 show the eight possible modes. The TRISA and TRISC registers control the data direction of the comparator output pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 15.0 “Electrical Specifications”. FIGURE 7-3: COMPARATOR I/O OPERATING MODES FOR PIC12F635 Note: Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur. Comparator Reset (POR Default Value – Low Power) Comparator Off (Lowest Power)(1) CM<2:0> = 000 CM<2:0> = 111 Comparator without Output Comparator w/o Output and with Internal Reference CM<2:0> = 010 CM<2:0> = 100 Comparator with Output and Internal Reference Multiplexed Input with Internal Reference and Output CM<2:0> = 011 CM<2:0> = 101 Comparator with Output Multiplexed Input with Internal Reference CM<2:0> = 001 CM<2:0> = 110 Legend: A = Analog Input, ports always read ‘0’ CIS = Comparator Input Switch (CMCON0<3>) D = Digital Input Note 1: Lowest power statement assures valid digital stats on GPO, GP1 and GP2. GP1/CIN- GP0/CIN+ Off (Read as ‘0’) A A GP2/C1OUT D GP1/CIN- GP0/CIN+ Off (Read as ‘0’) D D GP2/C1OUT D GP1/CIN- GP0/CIN+ C1OUT A A GP2/C1OUT D GP1/CIN- GP0/CIN+ C1OUT A D GP2/C1OUT D From CVREF Module GP1/CIN- GP0/CIN+ C1OUT A D GP2/C1OUT D From CVREF Module GP1/CIN- GP0/CIN+ C1OUT A A GP2/C1OUT D From CVREF Module CIS = 0 CIS = 1 GP1/CIN- GP0/CIN+ C1OUT A A GP2/C1OUT D GP1/CIN- GP0/CIN+ C1OUT A A GP2/C1OUT D From CVREF Module CIS = 0 CIS = 1 |
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