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VSC8140 bảng dữ liệu(PDF) 3 Page - Vitesse Semiconductor Corporation

tên linh kiện VSC8140
Giải thích chi tiết về linh kiện  2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
PDF  34 Pages
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nhà sản xuất  VITESSE [Vitesse Semiconductor Corporation]
Trang chủ  http://www.vitesse.com
Logo VITESSE - Vitesse Semiconductor Corporation

VSC8140 bảng dữ liệu(HTML) 3 Page - Vitesse Semiconductor Corporation

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© VITESSE SEMICONDUCTOR CORPORATION
Page 3
9/6/00
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8140
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
G52251-0, Rev. 4.0
Figure 2: Enabling FIFO Operation
Figure 3: DC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs
Figure 4: DC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs
Minimum 5 CLK16 cycles
FIFO Mode Operation
Transparent Mode Operation
Holding RESET “low” for a minimum of 5 CLK16 cycles, then setting “high” enables FIFO operation.
Holding RESET constantly “low” bypasses the FIFO for transparent mode operation.
PLL locked to reference clock.
RESET
VSC8140
Zo
R2
R2
R1
R1
VEE
VCC
VCCR2 + VEER1
R1+R2
= VTERM
downstream
R1||R2 = ZO
Zo
Split-end equivalent termination is ZO to VTERM
R1 = 125
Ω R2 = 83Ω, Z
O=50Ω, VTERM= VCC-2V
VCC-2V
R1 =50
Ω
VSC8140
Zo
VCC-2V
R1 =50
Ω
downstream



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