GD25Q80CSIG datasheet(36/67 Pages) GIGADEVICE

36 / 67 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q80C

If the Security Registers Lock Bit (LB) is set to 1, the Security Registers will be permanently locked. Program Security

Registers command will be ignored.

Address

A23-A16

A15-A8

A7-A0

Security Registers 0

00H

Byte Address

Security Registers 1

00H

01H

Byte Address

Security Registers 2

00H

02H

Byte Address

Security Registers 3

00H

03H

Byte Address

Figure 33. Program Security Registers command Sequence Diagram

7.31.

Read Security Registers (48H)

The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-Byte

address (A23-A0) and a dummy Byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,

at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The

first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each

Byte of data is shifted out. Once the A7-A0 address reaches the last Byte of the register (Byte FFH), it will reset to 00H, the

command is completed by driving CS# high.

Address

A23-A16

A15-A8

A7-A0

Security Registers 0

00H

Byte Address

Security Registers 1

00H

01H

Byte Address

Security Registers 2

00H

02H

Byte Address

Security Registers 3

00H

03H

Byte Address

Command

42H

CS#

SCLK

9 10

28 29 30 31

23 22 21

24-bit address

42 43 44 45

46 47

50 51 52 53

54 55

CS#

SCLK

MSB

Data Byte 2

32 33 34 35

MSB

5 4

Data Byte 1

Data Byte 3

Data Byte 256

MSB

36 37 38 39

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