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B9946
Document #: 38-07077 Rev. *C
Page 2 of 5
Note:
1.
PD = Internal Pull-Down, PU = Internal Pull-Up.
Pin Description[1]
Pin
Name
PWR
I/O
Description
3, 4
TCLK(0,1)
I, PU
External Reference/Test Clock Input
26, 28, 30
QA(2:0)
VDDC
O
Clock Outputs
19, 21, 23
QB(2:0)
VDDC
O
Clock Outputs
10, 12, 14, 16
QC(0:3)
VDDC
O
Clock Outputs
5, 6, 7
DSEL(A:C)
I, PD
Divider Select Inputs. When HIGH, selects
÷2 input divider. When
LOW, selects
÷1 input divider.
1
TCLK_SEL
I, PD
TCLK Select Input. When LOW, TCLK0 clock is selected and when
HIGH TCLK1 is selected.
32
MR/OE#
I, PD
Output Enable Input. When asserted LOW, the outputs are enabled
and when asserted HIGH, internal flip-flops are reset and the out-
puts are three-stated.
9, 13, 17, 18, 22,
25, 29
VDDC
3.3V Power Supply for Output Clock Buffers
2
VDD
3.3V Power Supply
8, 11, 15, 20, 24,
27, 31
VSS
Common Ground
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