IP175G datasheet(30/69 Pages) ETC2

30 / 69 page

IP175G/GI/GH/GHI

Data Sheet

30 / 69

November 27, 2012

IP175Gx-DS-R01.3

R/W = Read/Write,

SC = Self-Clearing,

RO = Read Only,

LL = Latching Low,

LH = Latching High

Port 0 PHY address : 2 ;

Port 1 PHY address : 3 ;

Port 2 PHY address : 4 ;

Port 3 PHY address : 6 ;

Port 4 PHY address : 7 ;

6.1

MII Register

PHY

MII

R/W

Description

Default

Control Register

0.15

RW/

Reset

The PHY is reset if user writes “1” to this bit. The reset period is around

2ms. User has to wait for at least 2ms to access IP175G/GH.

0.14

R/W

Loop back

1 = Loop back mode

0 = normal operation

When this bit set, IP175G/GH will be isolated from the network media,

that is, the assertion of TXEN at the MII will not transmit data on the

network. All MII transmission data will be returned to MII receive data

path in response to the assertion of TXEN.

Bit 0.12 is cleared automatically, if this bit is set. User has to program

bit 0.12 again after loop back test.

0.13

Speed Selection

1 = 100Mbps

0 = 10Mbps

It is valid only if bit 0.12 is set to be 0.

0.12

Auto-Negotiation(AN) Enable

1 = Auto-Negotiation Enable

0 = Auto-Negotiation Disable

0.11

R/W

Power Down

1: power down mode

0: normal operation

0.10

Isolate

IP175G/GH doesn’t support this function.

0.9

Restart Auto-Negotiation

1 = re-starting Auto-Negotiation

0: normal operation

0.8

R/W

Duplex mode

1 = full duplex

0 = half duplex

It is valid only if bit 0.12 is set to be 0.

0.7

R/W Collision test

0[6:0]

RO Reserved

IP175G bảng dữ liệu(PDF) 30 Page - List of Unclassifed Manufacturers

IP175G bảng dữ liệu(HTML) 30 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

bảng dữ liệu tải về

Link URL