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FS7755-IS bảng dữ liệu(PDF) 4 Page - Fortune Semiconductor Corp. |
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FS7755-IS bảng dữ liệu(HTML) 4 Page - Fortune Semiconductor Corp. |
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4 / 22 page ![]() FS7755 Rev. 1.1 4/22 5. Pin Configuration Fig1 Pin Configuration 6. Pin Description Pin Name Function 1 DVDD Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the FS7755. The supply voltage should be maintained at 5V ± 5% for specified operation. This pin should be decoupled with a 10μF capacitor in parallel with a ceramic 100nF capacitor. 2, 4, 19 NC No Connect 3 AVDD Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the FS7755. The supply should be maintained at 5V ± 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. This pin should be decoupled to AGND with a 10μF capacitor in parallel with a ceramic 100nF capacitor. 5, 6 V1P, V1N Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with a maximum differential signal level of ±470mV for specified operation. Channel 1 also has a PGA, and the gain selections are outlined in Table I. The maximum signal level at these pins is ±1V with respect to AGND. Both inputs have internal ESD protection circuitry. An overvoltage of ±6V can be sustained on these inputs without risk of permanent damage. 7, 8 V2P, V2N Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differential input pair. The maximum differential input voltage is ±660mV for specified operation. The maximum signal level at these pins is ±1V with respect to AGND. Both inputs have internal ESD protection circuitry, and an over-voltage of ±6V can also be sustained on these inputs without risk of permanent damage. |
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