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FS98O21 bảng dữ liệu(PDF) 4 Page - Fortune Semiconductor Corp. |
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FS98O21 bảng dữ liệu(HTML) 4 Page - Fortune Semiconductor Corp. |
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4 / 136 page ![]() FS98O21 Rev. 1.7 4/136 5. CLOCK SYSTEM ..................................................................................................................................... 39 5.1 Oscillator State ............................................................................................................................ 40 5.2 CPU Instruction Cycle ................................................................................................................ 42 5.3 ADC Sample Frequency ............................................................................................................. 43 5.4 Beeper Clock ............................................................................................................................... 44 5.5 Voltage Doubler Operation Frequency ......................................................................................46 5.6 Chopper Operation Amplifier Input Control Signal ..................................................................47 5.7 TMCLK -- Timer and LCD Module Input Clock.......................................................................... 48 6. TIMER MODULE AND WATCH DOG TIMER...........................................................................................49 6.1 Timer Module............................................................................................................................... 51 6.1.1 Timer module interrupt ................................................................................................... 52 6.1.2 Using Timer with External/Internal Clock......................................................................53 6.2 Watch Dog Timer......................................................................................................................... 55 7. I/O PORT .................................................................................................................................................. 56 7.1 Digital I/O Port with Analog Input Channel Shared: PT1[7:0] ..................................................65 7.2 Digital I/O Port and External Interrupt Input : PT2[0], PT2[1] ..................................................66 7.3 Digital I/O Port or PDM Output : PT2[2] ..................................................................................... 69 7.4 Digital I/O Port or I2C Serial Port : PT2[3]/SDA, PT2[4]/SCL....................................................71 7.5 Digital I/O Port : PT2[6:5] ............................................................................................................ 73 7.6 Digital I/O Port or Buzzer Output : PT2[7] ................................................................................. 75 8. PDM (PULSE DENSITY MODULATOR) MODULE ..................................................................................77 9. I2C MODULE (SLAVE MODE ONLY) ...................................................................................................... 83 10. ANALOG FUNCTION NETWORK ........................................................................................................... 90 10.1 Analog to Digital Converter (ADC) : .......................................................................................... 99 10.2 OPAMP : OP1............................................................................................................................. 103 11. ADC APPLICATION GUIDE ................................................................................................................... 105 11.1 ADC Output Format .................................................................................................................. 105 11.2 ADC Linear Range.....................................................................................................................105 11.3 ADC Output Rate and Settling Time ........................................................................................105 11.4 ADC Input Offset ....................................................................................................................... 105 11.5 ADC Digital Output.................................................................................................................... 106 11.6 ADC Resolution......................................................................................................................... 106 12. LOW NOISE OPERATION AMPLIFIER GUIDE ..................................................................................... 107 12.1 Single End Amplifier Application............................................................................................. 107 12.2 Differential Amplifier ................................................................................................................. 108 13. LCD DRIVER .......................................................................................................................................... 109 14. HALT AND SLEEP MODES ................................................................................................................... 121 |
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