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MSM6789 bảng dữ liệu(PDF) 8 Page - OKI electronic componets |
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MSM6789 bảng dữ liệu(HTML) 8 Page - OKI electronic componets |
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8 / 53 page ![]() MSM6789A/6789L ¡ Semiconductor PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued) Symbol Type Description Mode Selection. Low level : Stand-alone mode High level : Microcontroller interface mode PDWN I Power Down. When a low level is input, the MSM6789A goes to the power down state. Unlike the RESET pin, this pin does not force the MSM6789A to be reset. When a Low level is applied to this pin during recording operation, the MSM6789A is halted, and will be maintained in the power down state while PDWN is low level. After this pin is restored to a high level, postprocessing for recording will be performed. Oscillator Connection. When an external clock is used, input the clock through this pin. During the power down state, this pin must be set to the ground level. XT I TEST MSM6789A Test. Input a low level to the TEST pin and a high level to the TEST pin. RSEL1 I TEST I RSEL2 I MSEL2 MSEL1 RSEL2 RSEL1 Memory capacity LLLL 4M ¥ 1 LLL H 4M ¥ 2 L LHL 4M ¥ 3 L L H H 4M ¥ 4 LHL L 8M ¥ 1 LHLH 8M ¥ 2 LH HL 8M ¥ 3 L HHH 8M ¥ 4 • When serial register is selected (DRAM/SR = Low level) MCUM I Oscillator Connection. When an external clock is used, this pin must be left open. XT O MSM6789A Test. This pin must be left open. TMD3-TMD0 TDT7-TDT0 SYNC I/O Connect these pins to DQ1-DQ4 of DRAM at the time of 4-bit ¥ type DRAM selection. Otherwise these pins must be left open as they are MSM6789A test pins. TDT3-TDT0 [DQ4]-[DQ1] I/O MSM6789A Test. Input a low level signal. TST TCK TMD4 I This pin selects CAS-before-RAS refresh period of DRAM at the time of power down when DRAM is selected. Low level : 15 µs max. High level : 125 µs max. LOWPWR I A high input level causes the MSM6789A to be initialized and to go into the power down state. RESET I Pin 60 91 56 37 57 34 92 9-12 17-20 22 87 62 13-20 23 21 8 61 |
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