AT2004
4 Channels ADPCM Processor with Echo Cancellation and Conferencing
Page 8 of 25
©2001 Atelic System, Inc
a. This command sequence also adjusts gain control
5.
Chip Power-up and Power-down commands.
PLL Command Sequence
The PLL Command Sequence is a 3-byte command sequence that sets the operating speed of the AT2004 to be a multiple of the input
crystal Mhz.
Format of PLL Command Sequence
Byte 1
0
1
F3
F2
F1
F0
A1
A0
Byte 2
N6
N5
N4
N3
N2
N1
N0
M5
Byte 3
M4
M3
M2
M1
M0
P2
P1
P0
A[1:0] refers to the chip ID (please refer to section talking about chip ID)
N[6:0] = n,
binary number used for frequency multiplier
M[5:0] = m,
binary number used for frequency divider
P[2:0] = table
specialized frequency divider (please refer to table).
F[3:0] = Divider for CLKP & CLKA Generator. f(CLKA/CLKP) = f(XTAL) / F[3:0]
Table for P, frequency multiplier
P = 0
Bypass, PLLclk = XTALclk regardless of N, M.
P = 1
16
P = 2
8
P = 3
4
P = 4
2
P = 5
1
P = 6
No PLLclk, PLLclk = 0 Hz (chip disabled!)
P = 7
No PLLclk, PLLclk = 0 Hz (chip disabled!)
The system clock uses N, M, and P to determine the speed of the system clock using the following formula:
System Clock = (Crystal_clk * N * 4) / (M * P)
By default, the chip is set to run at 86 Mhz using a 14.3 Mhz crystal input.
MCU7byte Command Sequence
This command sequence allows the user to specify the ADPCM algorithm, I/O bit-slots, delay and EC’s reference channel number. The
command sequence length is variable, and is dependent on the number of channels that are specified. The command sequence consists of
a header byte, a data portion consisting of 7 bytes for every channel specified, and a footer byte. The total number of bytes in the
command sequence will be 2+7N where N = number of half channels specified.
The channels should be sorted by the user in increasing order of ‘Input Begin Bit’. All the YIN channels should be placed in sorted order
before all the XIN channels.
Below is a sample of MCU7byte command sequence for two ‘half channels’.
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