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FM8PC71AMAEP bảng dữ liệu(PDF) 39 Page - Feeling Technology Corp. |
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FM8PC71AMAEP bảng dữ liệu(HTML) 39 Page - Feeling Technology Corp. |
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39 / 73 page ![]() FM8PC71AM This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product. P.39 R1.1.004, Aug 7, 2017 FM8PC71AM 遠翔科技 Feeling Technology Address 16H: PWM0 Timer Low byte value Register (P0TMLB) Bits 7 6 5 4 3 2 1 0 Name P0TM[7:0]/ Read/Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Name N0[7:0] Default 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Bit[7:0] : P0TM[7:0] PWM0 Timer Low byte read Only Bit[7:0] : N0[7:0] Divider parameter by (N0+1) for Fcpu/Firc/fosc write only, read by IOSTR. Address 16H: PWM0 Timer Divider parameter Register (N0) Bits 7 6 5 4 3 2 1 0 Name N0[7:0] Default 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Read only by IOSTR instruction Bit[7:0] : N0[7:0] Divider parameter by (N0+1) for Fcpu/Firc/fosc Read only Address 17H: PWM0 Timer compared or overflow reload Low byte value Register (P0RDLB) Bits 7 6 5 4 3 2 1 0 Name P0TRD[7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit[7:0] : P0TRD[7:0] PWM0 Timer compared or overflow reload Low byte Address 18H: PWM0 Timer and Reload High-nibble bits Register(P0TRHB) Bits 7 6 5 4 3 2 1 0 Name P0TM [11:8] P0TRD [11:8] Read/Write R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit[7:4] : P0TM[11:8] PWM0 Timer high-nibble bits Bit[3:0] : P0TRD [11:8] PWM0 Timer compared or overflow reload high-nibble bits. |
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