LD5760GS datasheet(16/20 Pages) LEADTREND

16 / 20 page

LD5760

11/05/2015

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD5760-DS-02 November 2015

GND

LD5760

This resistor would protect the MOSFET

from being false triggered by the current

through CGD, if RG is disconnected.

OUT

CGD

Cgd

bulk





VBULK

Fig. 20

Protection Resistor on the Hi-V Path

In some other Hi-V process and design, there may be a

parasitic SCR caused around HV pin, VCC and GND.

As shown in Fig. 21, a small negative spike on the HV

pin may trigger this parasitic SCR and cause latch-up

between VCC and GND.

It may damage the chip

because of the equivalent short-circuit induced by such

latch-up behavior.

Leadtrend’s proprietary of Hi-V technology will eliminate

parasitic SCR in LD5760.

Fig. 22 shows the equivalent

Hi-V structure circuit of LD5760.

So that LD5760 is

more capable to sustain negative voltage than similar

products. However, a 10K

 resistor is recommended to

add in the Hi-V path to play as a current limit resistor

as a negative voltage is applied.

VCC

GND

Other HV process with

parasitic SCR

Negative-triggered Parasitic SCR.

Small negative spike on HV pin will cause

the latchup between Vcc and GND.

Fig. 21

VCC

GND

Parasitic effect

between HV, Vcc and

GND

Current limit resistor for

Preventing damage from

Negative voltage

(recommended)

Fig. 22

Output Over Voltage Protection (CS Pin) -

Auto Recovery

An output overvoltage protection is implemented in the

LD5760, as shown in Fig. 23 and 24. The auxiliary

winding voltage is reflected to secondary winding and

therefore the flat voltage on the CS pin is proportional to

the output voltage. By sensing the auxiliary voltage via

the divided resistors, LD5760 can sample this flat

voltage level after some delay time to perform output

over-voltage protection. This delay time is used to

ignore the voltage ringing from leakage inductance of

PWM transformer. The sampling voltage level is

compared with internal threshold voltage VCSOVP. If the

sampling voltage exceeds the OVP trip level, an internal

counter starts counting subsequent OVP events. The

counter has been added to prevent incorrect OVP

detection which might occur during ESD or lightning

events. However, if typically 10 cycles of subsequent

LD5760GS bảng dữ liệu(PDF) 16 Page - Leadtrend Technology

LD5760GS bảng dữ liệu(HTML) 16 Page - Leadtrend Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

bảng dữ liệu tải về

Link URL