KSZ8463RL datasheet(7/259 Pages) MICREL

7 / 259 page

Micrel, Inc.

KSZ8463ML/RL/FML/FRL

June 11, 2014

Revision 1.0

“Receive Only” Mirror-on-a-Port .................................................................................................................................... 43

“Transmit Only” Mirror-on-a-Port ................................................................................................................................... 43

“Receive and Transmit” Mirror-on-Two-Ports ................................................................................................................ 43

IEEE 802.1Q VLAN Support .......................................................................................................................................... 43

Quality-of-Service (QoS) Priority Support ......................................................................................................................... 44

Port-Based Priority ............................................................................................................................................................ 44

802.1p-Based Priority ........................................................................................................................................................ 44

802.1p Priority Field Re-Mapping ...................................................................................................................................... 45

DiffServ-Based Priority ...................................................................................................................................................... 45

Rate Limiting Support ........................................................................................................................................................ 45

MAC Address Filtering Function........................................................................................................................................ 46

IEEE 1588 Precision Time Protocol (PTP) Block.................................................................................................................. 47

IEEE 1588 PTP Clock Types............................................................................................................................................. 48

IEEE 1588 PTP One-Step or Two-Step Clock Operation ................................................................................................. 48

IEEE 1588 PTP Best Master Clock Selection ................................................................................................................... 48

IEEE 1588 PTP System Time Clock ................................................................................................................................. 48

Updating the System Time Clock ...................................................................................................................................... 50

Directly Setting or Reading the Time ............................................................................................................................. 50

Step-Time Adjustment ................................................................................................................................................... 50

Continuous Time Adjustment......................................................................................................................................... 50

Temporary Time Adjustment ......................................................................................................................................... 50

PTP Clock Initialization .................................................................................................................................................. 51

IEEE 1588 PTP Message Processing ............................................................................................................................... 51

IEEE 1588 PTP Ingress Packet Processing .................................................................................................................. 51

IEEE 1588 PTP Egress Packet Processing................................................................................................................... 51

IEEE 1588 PTP Event Triggering and Timestamping ....................................................................................................... 52

IEEE 1588 PTP Trigger Output ..................................................................................................................................... 52

IEEE 1588 PTP Event Timestamp Input........................................................................................................................ 52

IEEE 1588 PTP Event Interrupts ................................................................................................................................... 53

IEEE 1588 GPIO ............................................................................................................................................................ 53

General Purpose and IEEE 1588 Input/Output (GPIO) ........................................................................................................ 54

Overview............................................................................................................................................................................ 54

GPIO Pin Functionality Control.......................................................................................................................................... 54

GPIO Pin Control Register Layout..................................................................................................................................... 55

GPIO Trigger Output Unit and Timestamp Unit Interrupts ................................................................................................ 57

Using the GPIO Pins with the Trigger Output Units .............................................................................................................. 59

Creating a Low-Going Pulse at a Specific Time................................................................................................................ 59

Creating a High-Going Pulse at a Specific Time ............................................................................................................... 59

Creating a Free Running Clock Source............................................................................................................................. 60

Creating Finite Length Periodic Bit Streams at a Specific Time........................................................................................ 61

Creating Finite Length Non-Uniform Bit Streams at a Specific Time ................................................................................ 61

Creating Complex Waveforms at a Specific Time............................................................................................................. 62

Using the GPIO Pins with the Timestamp Input Units .......................................................................................................... 64

Device Clocks........................................................................................................................................................................ 66

GPIO and IEEE 1588-Related Clocking............................................................................................................................ 67

Power .................................................................................................................................................................................... 68

Internal Low Voltage LDO Regulator................................................................................................................................. 69

Power Management .............................................................................................................................................................. 70

Normal Operation Mode .................................................................................................................................................... 70

Energy-Detect Mode.......................................................................................................................................................... 70

Global Soft Power-Down Mode ......................................................................................................................................... 71

Energy-Efficient Ethernet (EEE) ........................................................................................................................................ 71

Transmit Direction Control for MII Mode ........................................................................................................................... 72

Receive Direction Control for MII Mode ............................................................................................................................ 72

Registers Associated with EEE ......................................................................................................................................... 72

Interrupt Generation on Power Management-Related Events.............................................................................................. 72

Interfaces............................................................................................................................................................................... 73

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