PIC18F4520ESLASHMLQTP datasheet(281/390 Pages) MICROCHIP

281 / 390 page

 2004 Microchip Technology Inc.

Preliminary

DS39631A-page 279

PIC18F2420/2520/4420/4520

BRA

Unconditional Branch

Syntax:

BRA

Operands:

-1024

≤ n ≤ 1023

Operation:

(PC) + 2 + 2n

→ PC

Status Affected:

None

Encoding:

1101

0nnn

nnnn

Description:

Add the 2’s complement number ‘2n’ to

the PC. Since the PC will have incre-

mented to fetch the next instruction, the

new address will be PC + 2 + 2n. This

instruction is a two-cycle instruction.

Words:

Cycles:

Q Cycle Activity:

Decode

Read literal

‘n’

Process

Data

Write to PC

operation

Example:

HERE

BRA

Jump

Before Instruction

address (HERE)

After Instruction

address (Jump)

BSF

Bit Set f

Syntax:

BSF

f, b {,a}

Operands:

≤ f ≤ 255

≤ b ≤ 7

∈ [0,1]

Operation:

→ f<b>

Status Affected:

None

Encoding:

1000

bbba

ffff

Description:

Bit ‘b’ in register ‘f’ is set.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write

Example:

BSF

FLAG_REG, 7, 1

Before Instruction

FLAG_REG

0Ah

After Instruction

FLAG_REG

8Ah

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