PIC18F4520ESLASHMLQTP datasheet(277/390 Pages) MICROCHIP

277 / 390 page

 2004 Microchip Technology Inc.

Preliminary

DS39631A-page 275

PIC18F2420/2520/4420/4520

ANDWF

AND W with f

Syntax:

ANDWF

f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(W) .AND. (f)

→ dest

Status Affected:

N, Z

Encoding:

0001

01da

ffff

Description:

The contents of W are AND’ed with

in W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

ANDWF

REG,

0, 0

Before Instruction

17h

REG

C2h

After Instruction

02h

REG

C2h

Branch if Carry

Syntax:

Operands:

-128

≤ n ≤ 127

Operation:

if CARRY bit is ‘1’

(PC) + 2 + 2n

→ PC

Status Affected:

None

Encoding:

1110

0010

nnnn

Description:

If the CARRY bit is ‘1’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Decode

Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

‘n’

Process

Data

operation

Example:

HERE

Before Instruction

address (HERE)

After Instruction

If CARRY

address (HERE + 12)

If CARRY

address (HERE + 2)

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