NE555G-S08-R datasheet(5/7 Pages) UTC

5 / 7 page

NE555

LINEAR INTEGRATED CIRCUIT

UNISONICTECHNOLOGIESCO.,LTD

5 of 7

www.unisonic.com.tw

QW-R106-001.G

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TYPICAL APPLICATION NOTES

The application circuit shows astable mode configuration.

Pin 6 (Threshold ) is tied to Pin 2 ( Trigger ) and Pin 4 ( reset ) is tied to VCC ( Pin 8 ). The external capacitor C1 of

Pin 6 and Pin 2 charges through RA, RB and dischages through RB only. In the internal circuit of UTC NE555N , one

input of the upper comparator is at voltage of 2/3VCC (R1=R2=R3),another input is connected to Pin 6.As soon as C1

is charging to higher than 2/3VCC, transistor Q1 is turned ON and discharge C1 to collector voltage of transistor Q1.

Therefore, the flip-flop circuit is reset and output is low. One input of lower comparator is at voltage of 1/3Vcc,

discharge transistor Q1 turn off and C1 charges through RA and RB. Therefore, the flip-flop circuit is set output high.

That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB ,output is low.

The charge time(output is high) t1 is 0.693(RA+RB) C1 and the discharge time (output is low) T2 is 0.693 RB×C1.

0.693

T1=0.693×(RA+RB)×C1

Thus the total period time T is given by

T2=0.693×RB×C1

T=T1+T2=0.693(RA+2RB)×C1.

Then the frequency of astable mode is given by

11.44

T(R + 2R ) C1

The duty cycle is given by

D.C.

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