4256BWP datasheet(10/25 Pages) STMICROELECTRONICS

10 / 25 page

M24128-BW, M24128-BR, M24256-BW, M24256-BR

10/25

Figure 8. Write Cycle Polling Flowchart using ACK

Minimizing System Delays by Polling On ACK

During the internal Write cycle, the device discon-

nects itself from the bus, and writes a copy of the

data from its internal latches to the memory cells.

The maximum Write time (tw) is shown in Table

14. and Table 15., but the typical time is shorter.

To make use of this, a polling sequence can be

used by the bus master.

The sequence, as shown in Figure 8., is:

–

Initial condition: a Write cycle is in progress.

–

Step 1: the bus master issues a Start condition

followed by a Device Select Code (the first

byte of the new instruction).

–

Step 2: if the device is busy with the internal

Write cycle, no Ack will be returned and the

bus master goes back to Step 1. If the device

has terminated the internal Write cycle, it

responds with an Ack, indicating that the

device is ready to receive the second part of

the instruction (the first byte of this instruction

having been sent during Step 1).

WRITE Cycle

in Progress

AI01847C

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

ReSTART

STOP

DATA for the

WRITE Operation

DEVICE SELECT

with RW = 1

Send Address

and Receive ACK

First byte of instruction

with RW = 0 already

decoded by the device

YES

START

Condition

Continue the

WRITE Operation

Continue the

Random READ Operation

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