AD5380EB datasheet(8/34 Pages) AD

8 / 34 page

PRELIMINARY TECHNICAL DATA

REV. PrF 09/2003

–8–

AD5380

F SCL

400

kHz max

SCL Clock Frequency

2.5

µs min

SCL Cycle Time

0.6

µs min

tHIGH, SCL High Time

1.3

µs min

tLOW, SCL Low Time

0.6

µs min

tHD,STA, Start/Repeated Start Condition Hold Time

100

ns min

tSU,DAT, Data Setup Time

0.9

µs max

tHD,DAT, Data Hold Time

µs min

tHD,DAT, Data Hold Time

0.6

µs min

tSU,STA, Setup Time for Repeated Start

0.6

µs min

tSU,STO, Stop Condition Setup Time

1.3

µs min

tBUF, Bus Free Time Between a STOP and a START Condition

t10

300

ns max

tR, Rise Time of SCL and SDA when Receiving

ns min

tR, Rise Time of SCL and SDA when Receiving (CMOS-Com

patible)

t11

300

ns max

tF, Fall Time of SDA when Transmitting

ns min

tF, Fall Time of SDA when Receiving (CMOS-Compatible)

300

ns max

tF, Fall Time of SCL and SDA when Receiving

20 + 0.1Cb

ns min

tF, Fall Time of SCL and SDA when Transmitting

C B

400

pF max

Capacitive Load for Each Bus Line

TIMING CHARACTERISTICS

(DVDD= 2.7V to 5.5V ; AVDD=+4.5V to +5.5V or +2.7V to +3.6V; AGND= DGND = 0 V; )

All specifications TMIN to TMAX unless otherwise noted.)

I2C SERIAL INTERFACE

Parameter

1,2

Limit at TMIN, TMAX

Units

Description

NOTES

1Guaranteed by design and characterization, not production tested.

2See Figure 5

3A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V

IH MIN of the SCL signal) in order to bridge the

undefined region of SCL’s falling edge.

4Cb is the total capacitance of one bus line in pF. t

R and tF measured between 0.3 VDD and 0.7 VDD.

SCL

SDA

START

CONDITION

t11

t10

REPEATED

START

CONDITION

STOP

CONDITION

Figure 5. I2C Compatible Serial Interface Timing Diagram

AD5380EB bảng dữ liệu(PDF) 8 Page - Analog Devices

AD5380EB bảng dữ liệu(HTML) 8 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

bảng dữ liệu tải về

Link URL