ATSAM3303 datasheet(19/25 Pages) ATMEL

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ATSAM3303

6091A–DRMSD–07/04

External Memory

Pins used: WA21 - WA0: address out, WD15 - WD0: data bi-directional, WCS0, WCS1:

pre-decodes out, WOE: output enable, WWE: write

When using all address bits, the maximum address range is two pages (WCS0, WCS1)

of 4M words (total = 16 Mbytes).

Figure 12. ROM/Flash Read Cycle

Notes:

1. A built-in PLL multiplies the crystal clock frequency by 4 for internal use. p

LCK is the period of the internal clock generated by

PLL. p

LCK = tCK/4. Typical value with crystal 12.288 MHz is pLCK = 20 ns.

2. Memory access time should be lower than t

ACEmin. Typical value with crystal 12.288 MHz is 90 ns.

tRC

tCSOE

tPOE

tACE

tOE

tDF

WA0 - WA21

WD0 - WD15

WCS0

WOE

WCS1

Table 10. External Memory Parameters

Symbol

Parameter

Min

Typ

Max

Unit

Read cycle time

5 * p

LCK

-6 * p

LCK

CSOE

Chip select low/address valid to WOE low

2 * p

LCK - 5

3 * p

LCK + 5

POE

Output enable pulse width

3 * p

LCK

-ns

ACE

Chip select/address access time

5 * p

LCK - 5

Output enable access time

3 * p

LCK - 5

Chip select or WOE high to input data Hi-Z

2 * p

LCK - 5

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