2003 Dec 08

2

Philips Semiconductors

Product specification

16-bit D-type transparent latch with 5 V

tolerant inputs/outputs; 3-state

74LVC16373A;

74LVCH16373A

FEATURES

• 5 V tolerant inputs/outputs for interfacing with 5 V logic

• Wide supply voltage range from 1.2 to 3.6 V

• CMOS low power consumption

• MULTIBYTE flow-through standard pin-out architecture

• Low inductance multiple power and ground pins for

minimum noise and ground bounce

• Direct interface with TTL levels

• All data inputs have bushold (74LVCH16373A only)

• Complies with JEDEC standard no. 8-1A

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION

The 74LVC(H)16373A is a 16-bit D-type transparent latch

featuring separate D-type inputs for each latch and 3-state

outputs for bus oriented applications. One Latch Enable

(LE) input and one Output Enable (OE) are provided for

each octal. Inputs can be driven from either 3.3 or 5 V

devices. In 3-state operation, outputs can handle 5 V.

These features allow the use of these devices in a mixed

3.3 and 5 V environment.

The 74LVC(H)16373A consists of 2 sections of eight

D-type transparent latches with 3-state true outputs. When

LE is HIGH, data at the Dn inputs enter the latches. In this

condition the latches are transparent, i.e., a latch output

will change each time its corresponding D-input changes.

When LE is LOW the latches store the information that was

present at the D-inputs a set-up time preceding the

HIGH-to-LOW transition of LE. When OE is LOW, the

contents of the eight latches are available at the outputs.

When OE is HIGH, the outputs go to the high impedance

OFF-state. Operation of the OE input does not affect the

state of the latches.

The 74LVCH16373A bushold data inputs eliminates the

need for external pull up resistors to hold unused inputs.

FUNCTION TABLE

Per section of eight bits; note 1

Note

1. H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;

Z = high-impedance OFF-state.

OPERATING MODES

INPUT

INTERNAL

LATCHE

OUTPUT

nQ0tonQ7

nOE

nLE

nDn

Enable and read register (transparent mode)

L

H

L

L

L

L

HHHH

Latch and read register

L

L

l

L

L

LLh

H

H

Latch register and disable outputs

H

L

l

L

Z

HL

hH

Z