ZXLD1350Q datasheet(12/21 Pages) DIODES

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ZXLD1350Q

Document number: DS37076 Rev. 2 - 2

12 of 21

www.diodes.com

September 2017

ZXLD1350Q

Application Information (Cont.)

Low Frequency PWM Mode

When the ADJ pin is driven with a low frequency PWM signal (eg 100Hz), with a high level voltage VADJ and a low level of zero, the output of the

internal low pass filter will swing between 0V and VADJ, causing the input to the shutdown circuit to fall below its turn-off threshold (200mV nom)

when the ADJ pin is low. This will cause the output current to be switched on and off at the PWM frequency, resulting in an average output current

IOUTavg proportional to the PWM duty cycle. (See Figure 2 - Low frequency PWM operating waveforms).

Figure 2. Low frequency PWM operating waveforms

Figure 2. Low Frequency PWM Operating Waveforms

The average value of output current in this mode is given by:

IOUTavg = 0.1DPWM/RS

for DPWM >0. 01

This mode is preferable if optimum LED 'whiteness' is required. It will also provide the widest possible dimming range (approx. 100:1) and higher

efficiency at the expense of greater output ripple.

Note that the low pass filter introduces a small error in the output duty cycle due to the difference between the start-up and shut-down time. This

time difference is a result of the 200mV shutdown threshold and the rise and fall times at the output of the filter. To minimize this error, the PWM

duty cycle should be as low as possible consistent with avoiding flicker in the LED.

tON

tOFF

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