May 2012

© 1983 Fairchild Semiconductor Corporation

www.fairchildsemi.com

MM74HC86 • Rev. 1.4.0

MM74HC86

Quad 2-Input Exclusive OR Gate

Features

Figure 1.

Pin Assignments (Top View)

Description

The MM74HC86 exclusive OR gate utilizes advanced

silicon-gate CMOS technology to achieve operating

speeds similar to equivalent LS-TTL gates, while

maintaining the low power consumption and high noise

immunity characteristic of standard CMOS integrated

circuits. These gates are fully buffered and have a

fanout of 10 LS-TTL loads. The 74HC logic family is

functionally as well as pin-out compatible with the

standard 74LS logic family. All inputs are protected from

damage due to static discharge by internal diode clamps

Table 1.

Truth Table

Inputs

Outputs

A

B

Y

(1)

L

L

L

L

H

H

H

L

H

H

H

L

Note:

1.

B

A

B

A

B

A

Y









Ordering Information

Part Number

Operating

Temperature Range

Package

Packing Method

MM74HC86M

-40 to +85°C

14-Lead, Small Outline Integrated Circuit

(SOIC), JEDEC MS-012, 0.150" Narrow

Tube

MM74HC86MX

Tape & Reel

MM74HC86MTC

14-Lead, Thin Shrink Small Outline Package

(TSSOP), JEDEC MO-153, 4.4mm Wide

Tube

MM74HC86MTCX

Tape & Reel

Note:

2.

Pb-Free package per JEDEC J-STD-020B.