S93WD663S-B datasheet(3/14 Pages) SUMMIT

3 / 14 page

S93WD662/S93WD663

2013 2.1 8/2/00

2013 ILL 3 1.0

t DIS

PD0,

PD1

tCSMIN

tCSS

tDIS

tDIH

tSKHI

t CSH

VALID

DATA V ALID

t SKLOW

The ready/busy status can be determined after the start

of a write operation by selecting the device (CS high)

and polling the DO pin; DO low indicates that the write

operation is not completed, while DO high indicates that

the device is ready for the next instruction. See the

Applications Aid section for detailed use of the ready

busy status.

The format for all instructions is: one start bit; two op

code bits and either eight (x16) or nine (x8) address or

instruction bits.

Read

Upon receiving a READ command and an address

(clocked into the DI pin), the DO pin of the S93WD662/

WD663 will come out of the high impedance state and,

will first output an initial dummy zero bit, then begin

shifting out the data addressed (MSB first). The output

data bits will toggle on the rising edge of the SK clock and

are

stable

after

the

specified

time

delay

(tPD0 or tPD1).

Write

After receiving a WRITE command, address and the

data, the CS (Chip Select) pin must be deselected for a

minimum of 250ns (tCSMIN). The falling edge of CS will

start automatic erase and write cycle to the memory

location specified in the instruction. The ready/busy

status of the S93WD662/WD663 can be determined by

selecting the device and polling the DO pin.

Erase

Upon receiving an ERASE command and address, the

CS (Chip Select) pin must be deselected for a minimum

of 250ns (tCSMIN). The falling edge of CS will start the

auto erase cycle of the selected memory location. The

ready/busy status of the S93WD662/WD663 can be

Figure 1. Sychronous Data Timing

Figure 2. Read Instruction Timing

2013 ILL4 1.0

tCS

STANDBY

tHZ

HIGH-Z

AN–1

DN DN–1

tPD0

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