LTC2480CDD datasheet(20/40 Pages) LINER

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LTC2480

2480f

temperature dependent offset error due to the input

leakage current. A 1nA input leakage current will develop

a 1ppm offset error on a 5k resistor if VREF = 5V. This error

has a very strong temperature dependency.

SERIAL INTERFACE TIMING MODES

The LTC2480’s 4-wire interface is SPI and MICROWIRE

compatible. This interface offers several flexible modes of

operation. These include internal/external serial clock,

3- or 4-wire I/O, single cycle or continuous conversion.

The following sections describe each of these serial inter-

face timing modes in detail. In all these cases, the con-

verter can use the internal oscillator (FO = LOW or FO =

HIGH) or an external oscillator connected to the FO pin.

Refer to Table 6 for a summary.

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 5.

The serial clock mode is selected on the falling edge of CS.

To select the external serial clock mode, the serial clock pin

(SCK) must be LOW during each CS falling edge.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is pulled LOW, EOC is output to the SDO pin.

EOC = 1 while a conversion is in progress and EOC = 0 if

the device is in the sleep state. Independent of CS, the

device automatically enters the low power sleep state once

the conversion is complete.

When the device is in the sleep state, its conversion result

is held in an internal static shift register. The device

remains in the sleep state until the first rising edge of SCK

is seen while CS is LOW. The input data is then shifted in

via the SDI pin on the rising edge of SCK (including the

first rising edge) and the output data is shifted out of the

SDO pin on each falling edge of SCK. This enables

external circuitry to latch the output on the rising edge of

SCK. EOC can be latched on the first rising edge of SCK

and the last bit of the conversion result can be latched on

the 24th rising edge of SCK. On the 24th falling edge of

SCK, the device begins a new conversion. SDO goes HIGH

(EOC = 1) indicating a conversion is in progress. In

applications where the processor generates 32 clock

cycles, or to remain compatible with higher resolution

converters, the LTC2480’s digital interface will ignore

extra clock edges seen during the next conversion period

after the 24th and outputs “1” for the extra clock cycles.

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to Hi-Z.

As described above, CS may be pulled LOW at any time in

order to monitor the conversion status.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first rising edge and the 24th

falling edge of SCK (see Figure 6). On the rising edge of CS,

the device aborts the data output state and immediately

initiates a new conversion. If the device has not finished

loading the last input bit SPD of SDI by the time CS is pulled

HIGH, the SDI information is discarded and the previous

configuration is kept. This is useful for systems not requir-

ing all 24 bits of output data, aborting an invalid conversion

cycle or synchronizing the start of a conversion.

APPLICATIO S I FOR ATIO

Table 6. LTC2480 Interface Timing Modes

CONVERSION

DATA

CONNECTION

SCK

CYCLE

OUTPUT

and

CONFIGURATION

SOURCE

CONTROL

WAVEFORMS

External SCK, Single Cycle Conversion

External

CS and SCK

Figures 5, 6

External SCK, 3-Wire I/O

External

SCK

Figure 7

Internal SCK, Single Cycle Conversion

Internal

↓

Figures 8, 9

Internal SCK, 3-Wire I/O, Continuous Conversion

Internal

Continuous

Internal

Figure 10

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