COP8-NSDEV datasheet(16/83 Pages) NSC

16 / 83 page

9.0 Pin Descriptions (Continued)

Speed Oscillator Output)

L0 Multi-Input Wake-up (Low Speed Oscillator Input)

9.1 EMULATION CONNECTION

Connection to the emulation system is made viaa2x7

connector which interrupts the continuity of the RESET, G0,

G1, G2 and G3 signals between the COP8 device and the

rest of the target system (as shown in Figure 5). This con-

nector can be designed into the production PC board and

can be replaced by jumpers or signal traces when emulation

is no longer necessary.

The emulator will replicate all functions of G0 - G3 and

Reset. For proper operation, no connection should be made

on the device side of the emulator connector.

10.0 Functional Description

The architecture of the device is a modified Harvard archi-

tecture. With the Harvard architecture, the program memory

(Flash) is separate from the data store memory (RAM). Both

Program Memory and Data Memory have their own separate

addressing space with separate address buses. The archi-

tecture, though based on the Harvard architecture, permits

transfer of data from Flash Memory to RAM.

10.1 CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (t

C) cycle time.

There are six CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally

post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be

optionally post auto incremented or decremented.

S is the 8-bit Data Segment Address Register used to extend

the lower half of the address range (00 to 7F) into 256 data

segments of 128 bytes each.

SP is the 8-bit stack pointer, which points to the subroutine/

interrupt stack (in RAM). With reset the SP is initialized to

RAM address 06F Hex. The SP is decremented as items are

pushed onto the stack. SP points to the next available loca-

tion on the stack.

All the CPU registers are memory mapped with the excep-

tion of the Accumulator (A) and the Program Counter (PC).

20006306

FIGURE 2. I/O Port Configurations

20006307

FIGURE 3. I/O Port Configurations — Output Mode

20006308

FIGURE 4. I/O Port Configurations — Input Mode

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FIGURE 5. Emulation Connection

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