AX88875AP Bripeater

ASIX ELECTRONICS CORPORATION

11

2.4 Miscellaneous

Signal Name

Type Pin No.

Description

LCLK

I

133

Local Clock : Must be run at 25Mhz . Used for transmit data to PHY devices,

/RST

I

131

Reset : The chip is reset when this signal is asserted Low.

NC

or

/LSEL10

I/PU

110

NC : No Connection When MODE=”1”.

/LSEL10 : When MODE=”0” , This pin select 10Mbps global LED status

(

LED status is selected.

NC

or

/LCOL10

O/ML

111

NC : No Connection When MODE=”1”.

/LCOL : When MODE=”0” , This pin drives 10Mbps collision LED directly.

MCLK

O

72

MII Clock Out : 2.5MHz 10Mbps MII reference clock

MDO

O

71

Station Management Data Out : For setup PHY auto-negotiation registers.

A burst write commands are issue to setup PHY register after reset. The PHY

address 4h, 5h, 6h, 7h, 8h, 9h,Ah and Bh will be written as register 4h to

value 00A1h ( Advertise register set to 10/100 half-duplex mode)and register

0h to value 1000h(Enable auto-negotiation).

MDC

O

70

Station Management Data Clock Out : For MDO reference clock.

TEST1

I/PD

130

Test Pin : The pin is just for test mode setting purpose only. Must be pull low

when normal operation.

/TEST2

I/PU

114

Test Pin : The pin is just for test mode setting purpose only. Must be pull high

when normal operation.

/HALF10

I/PU

134

Half-duplex mode in 10Mbps : Pull low with 10K ohm resister for 10Mbps

PHY in half-duplex mode.

PULL_DN

I

11, 12, 46

136, 137

Pull Down : Those pins are not use for application. Designer must pull them

down or tie to ground.

SET2, SET1,

SET0

O

49, 48,

47

Setup Pins : Those pins are power on configuration use. Default internal pull

high. If necessary, pull low with 10K ohm resister. Tie to ground is

prohibited.

VDD

I

1, 13, 38

50, 55, 81

103, 109

125, 135

138

POWER : +5V +/-5%

VSS

I

10, 14, 29

45, 54, 68

89, 98,

108, 120,

132, 139

148,

POWER: 0V