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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HT95C30P bảng dữ liệu(PDF) 14 Page - Holtek Semiconductor Inc |
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HT95C30P bảng dữ liệu(HTML) 14 Page - Holtek Semiconductor Inc |
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14 / 52 page  HT95LXXX Rev. 1.20 14 May 26, 2004 status register may yield different results from those in- tended. The TO flag can be affected only by system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automati- cally pushed onto the stack. If the contents of the status are important and if the sub- routine can corrupt the status register, precautions must be taken to save it . Interrupt The telephone controller provides an external interrupt, internal timer/event counter interrupt, an internal real time clock interrupt and internal dialer I/O interrupt. The Interrupt Control Registers 0 and Interrupt Control Reg- ister 1 both contains the interrupt control bits that set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by hardware clearing the EMI bit). This scheme may prevent any further interrupt nest- ing. Other interrupt requests may occur during this inter- val but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 (INTC1) may be set to allow interrupt nesting. If the stack is full, any other interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate ser- vice is desired, the stack must be prevented from be- coming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro- gram memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. External interrupt is triggered by a high to low transition of the INT/TMR1 pin and the interrupt request flag EIF will be set. When the external interrupt is enabled, the stack is not full and the external interrupt is active, a sub- routine call to location 04H will occur. The interrupt re- quest flag EIF and EMI bits will be cleared to disable other interrupts. The Timer/Event Counter 0 interrupt is generated by a timeout overflow and the interrupt request flag T0F will be set. When the Timer/Event Counter 0 interrupt is en- abled, the stack is not full and the T0F bit is set, a sub- routine call to location 08H will occur. The interrupt request flag T0F and EMI bits will be cleared to disable further interrupts. The Timer/Event Counter 1 interrupt is generated by a timeout overflow and the interrupt request flag T1F will be set. When the Timer/Event Counter 1 interrupt is en- abled, the stack is not full and the T1F bit is set, a sub- Register Bits Label R/W Function INTC0 (0BH) 0 EMI RW Controls the master (global) interrupt (1=enabled; 0=disabled) 1 EEI RW Controls the external interrupt (1=enabled; 0=disabled) 2 ET0I RW Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) 3 ET1I RW Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) 4 EIF RW External interrupt request flag (1=active; 0=inactive) 5 T0F RW Timer/Event Counter 0 request flag (1=active; 0=inactive) 6 T1F RW Timer/Event Counter 1 request flag (1=active; 0=inactive) 7 ¾ RO Unused bit, read as ²0² INTC1 (1EH) 0 ¾ RW Reserved, inhibit using 1 ERTCI RW Control the real time clock interrupt (1=enable; 0=disable) 2 EDRI RW Control the dialer I/O interrupt (1=enable; 0=disable) 3 ¾ RO Unused bit, read as ²0² 4 ¾ RW Reserved, inhibit using 5 RTCF RW Internal real time clock interrupt request flag (1=active; 0=inactive) 6 DRF RW Internal dialer I/O interrupt request flag (1=active: 0=inactive) 7 ¾ RO Unused bit, read as ²0² |
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