HT95C30P datasheet(12/42 Pages) HOLTEK

12 / 42 page

HT95L100/10P

Rev. 0.10

October 1, 2002

Preliminary

Oscillator configuration

There are two oscillator circuits in the controller, the ex-

ternal 32768Hz crystal oscillator and internal WDT

OSC.

The 32768Hz crystal oscillator and frequency-up con-

version circuit (32768Hz to 3.58MHz) are designed for

dual system clock source. It is necessary for frequency

conversion circuit to add external RC components to

make up the low pass filter that stabilize the output fre-

quency 3.58MHz (see the oscillator circuit).

The WDT OSC is a free running on-chip RC oscillator,

and no external components are required. Even if the

system enters the Idle mode (the system clock is

stopped), the WDT OSC still works within a period of

ms normally. When the WDT is disabled or the WDT

source is not this RC oscillator, the WDT OSC will be

disabled.

Watchdog Timer

- WDT

The WDT clock source is implemented by a WDT OSC

or external 32768Hz or an instruction clock (system

clock divided by 4), determined by the mask option. This

timer is designed to prevent a software malfunction or

sequence from jumping to an unknown location with un-

predictable results. The Watchdog Timer can be dis-

abled by mask option. If the Watchdog Timer is disabled,

all the executions related to the WDT result in no opera-

tion.

If the device operates in a noisy environment, using the

on-chip WDT OSC or 32768Hz crystal oscillator is

strongly recommended.

When the WDT clock source is selected, it will be first di-

vided by 512 (9-stage) to get the nominal time-out

period. By invoking the WDT prescaler, longer time-out

periods can be realized. Writing data to WS2, WS1,

WS0 can give different time-out periods.

The WDT OSC period is 78

ms. This time-out period may

vary with temperature, VDD and process variations. The

WDT OSC always works for any operation mode.

If the instruction clock is selected as the WDT clock

source, the WDT operates in the same manner except

in the Sleep mode or Idle mode. In these two modes, the

WDT stops counting and lose its protecting purpose. In

this situation the logic can only be re-started by external

logic.

If the WDT clock source is the 32768Hz, the WDT also

operates in the same manner except in the Idle mode.

When in the Idle mode, the 32768Hz stops, the WDT

stops counting and lose its protecting purpose. In this

situation the logic can only be re-started by external

logic.

The high nibble and bit3 of the WDTS are reserved for

user defined flags, which can be used to indicate some

specified status.

The WDT time-out under Normal mode or Green mode

will initialize

²chip reset² and set the status bit ²TO². But

in the Sleep mode or Idle mode, the time-out will initial-

ize a

²warm reset² and only the program counter and

stack pointer are reset to 0. To clear the WDT contents

(including the WDT prescaler), three methods are

adopted; external reset (a low level to RES pin), soft-

ware instruction and a

²HALT² instruction.

The software instruction include

²CLR WDT² and the

other set

²CLR WDT1² and ²CLR WDT2². Of these two

types of instruction, only one can be active depending

on the mask option

²WDT instr².Ifthe ²CLR WDT² is se-

lected (i.e. One clear instruction), any execution of the

S y s t e m C l o c k / 4

9 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

M a s k

O p t i o n

S e l e c t

W D T O S C

3 2 7 6 8 H z

Watchdog Timer

X 1

X 2

X C

1 5 k W

3 n

5 0 n

System oscillator circuit

Label

Bits

R/W

Function

WDTS

(09H)

WS0

WS1

WS2

Watchdog Timer division ratio selection bits

Bit 2, 1, 0=000, Division ratio=1:1

Bit 2, 1, 0=001, Division ratio=1:2

Bit 2, 1, 0=010, Division ratio=1:4

Bit 2, 1, 0=011, Division ratio=1:8

Bit 2, 1, 0=100, Division ratio=1:16

Bit 2, 1, 0=101, Division ratio=1:32

Bit 2, 1, 0=110, Division ratio=1:64

Bit 2, 1, 0=111, Division ratio=1:128

7~3

Unused bit. These bits are read/write-able.

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