AD8021 datasheet(5/32 Pages) AD

5 / 32 page

AD5429/AD5439/AD5449

Rev. 0 | Page 5 of 32

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted.

See Figure 2 and Figure 3. Temperature range for Y version is −40°C to +125°C. Guaranteed by design and characterization, not subject to

production test. All input signals are specified with tr = tf = ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

Table 2.

Parameter

Limit at TMIN, TMAX

Unit

Conditions/Comments1

fSCLK

MHz max

Max clock frequency

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC falling edge to SCLK falling edge setup time

ns min

Data setup time

ns min

Data hold time

ns min

SYNC rising edge to SCLK falling edge

ns min

Minimum SYNC high time

ns min

SCLK falling edge to LDAC falling edge

t10

ns min

LDAC pulse width

t11

ns min

SCLK falling edge to LDAC rising edge

t122

ns min

SCLK active edge to SDO valid, strong SDO driver

ns min

SCLK active edge to SDO valid, weak SDO driver

1 Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.

2 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 4.

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