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LTC2633 bảng dữ liệu(PDF) 21 Page - Analog Devices |
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LTC2633 bảng dữ liệu(HTML) 21 Page - Analog Devices |
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21 / 24 page ![]() LTC2633 21 2633fc For more information www.linear.com/LTC2633 Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12 Bits). (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full Scale 2633 F05 INPUT CODE (b) OUTPUT VOLTAGE NEGATIVE OFFSET 0V 0V 2,048 0 4,095 INPUT CODE OUTPUT VOLTAGE (a) VREF = VCC VREF = VCC (c) INPUT CODE OUTPUT VOLTAGE POSITIVE FSE OPERATION internal reference command (0110b), any command in software that powers up the DACs will also power up the integrated reference. Voltage Output The LTC2633’s integrated rail-to-rail amplifier has guaran- teed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V. Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ω. The amplifier’s DC output impedance is 0.1Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50Ω typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is 50Ω • 1mA, or 50mV). See the graph Headroom at Rails vs Output Current in the Typical Performance Character- istics section. The amplifier is stable driving capacitive loads of up to 500pF. Rail-to-Rail Output Considerations Inanyrail-to-railvoltageoutputdevice,theoutputislimited to voltages within the supply range. SincetheanalogoutputoftheDACcannotgobelowground, it may limit for the lowest codes as shown in Figure 5b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 5c. No full-scale limiting can occur if VREF is less than VCC–FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. |
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