AD5686R datasheet(7/31 Pages) AD

7 / 31 page

Data Sheet

AD5686R/AD5685R/AD5684R

Rev. D | Page 7 of 31

17B

DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4

and Figure 5. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD =

2.7 V to 5.5 V.

Table 5.

1.62V ≤ VLOGIC < 2.7 V

2.7V ≤ VLOGIC ≤ 5.5 V

Parameter

17F

Symbol

Min

Max

Min

Max

Unit

SCLK Cycle Time

SCLK High Time

SCLK Low Time

SYNCEE

to SCLK Falling Edge

Data Setup Time

Data Hold Time

SCLK Falling Edge to

SYNCEE

Rising Edge

Minimum

SYNCEE

High Time

SDO Data Valid from SCLK Rising Edge

SYNCEE

Rising Edge to SCLK Falling Edge

t10

SYNCEE

Rising Edge to SDO Disable

t11

Guaranteed by design and characterization; not production tested.

42B

Circuit and Timing Diagrams

Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications

Figure 4. Daisy-Chain Timing Diagram

200µA

IOL

200µA

IOH

VOH (MIN)

TO OUTPUT

20pF

DB23

DB0

DB23

DB0

INPUT WORD FOR DAC N

UNDEFINED

INPUT WORD FOR DAC N + 1

INPUT WORD FOR DAC N

t10

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