AD5767 datasheet(32/43 Pages) AD

32 / 43 page

AD5766/AD5767

Data Sheet

Rev. C | Page 32 of 43

SERIAL INTERFACE

The AD5766/AD5767 4-wire (SYNC, SCLK, SDI, and SDO)

interface is compatible with SPI, QSPI, and MICROWIRE

interface standards as well as most digital signal processors

(DSPs). The write sequence begins after bringing the SYNC line

low, maintaining this line low until the complete data-word is

loaded from the SDI pin. Data is loaded into the AD5766/AD5767

at the SCLK falling edge transition (see Figure 2). When a rising

edge is detected on SYNC, the serial data-word is decoded

according to the instructions in Table 10. The command must

be a multiple of 24; otherwise, the device ignores the command.

The AD5766/AD5767 contain an SDO pin to allow the user to

daisy-chain multiple devices together or to read back the

contents of the status register.

Readback Operation

The contents of the status registers can be read back via the

SDO pin. Figure 4 shows how the registers are decoded. After a

clock the data out on the SDO pin. The clocks must be applied

while SYNC is low. For a read of a single register, the no

operation (NOP) function clocks out the data. Alternatively, if

more than one register is to be read, the data of the first register

to be addressed clocks out at the same time that the second

Daisy-Chain Operation

Daisy chaining minimizes the number of port pins required

from the controlling IC. As shown in Figure 72, the SDO pin of

one package must be tied to the SDI pin of the next package. To

enable daisy-chain mode, the DC_EN bit in Table 15 must be

high. When two AD5766/AD5767 devices are daisy-chained,

48 bits of data are required. The first 24 bits are assigned to U2,

and the second 24 bits are assigned to U1, as shown in Figure 72.

Keep the SYNC pin low until all 48 bits are clocked into their

respective serial registers.

The SYNC pin is then pulled high to complete the operation.

To prevent data from mislocking (for example, due to noise) the

device includes an internal counter; if the SCLK falling edges

count is not a multiple of 24, the device ignores the command.

A valid clock count is 24, 48, 72, and so on. The counter resets

when SYNC returns high.

Daisy-chain mode is disabled by default and is enabled using

the daisy-chain control register (see Table 15).

AD5766/

AD5767

SDI

SYNC SCLK

SCLK

SDO

AD5766/

AD5767

SDI

SYNC

SCLK

SDO

MICROCONTROLLER

MOSI

MISO

Figure 72. Daisy-Chain Block Diagram

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