Data Sheet

AD5693R/AD5692R/AD5691R/AD5693

Rev. D | Page 11 of 26

3

GND

4

A0

1

2

RESET

6 SDA

5 SCL

AD5693R-2

TOP VIEW

(Not to Scale)

NOTES

1. CONNECT THE EXPOSED PAD TO GND.

Figure 8. AD5693R-2 Pin Configuration, 8-Lead LFCSP, RESET Option

Table 10. AD5693R-2 Pin Function Descriptions, 8-Lead LFCSP, RESET Option

Pin No.

Mnemonic

Description

1

Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.

2

RESET

Hardware Reset Pin. The RESET input is low level sensitive. When RESET is low, the device is reset and external pins

are ignored. The input and DAC registers are loaded with zero code value and the control register is loaded with

does not initialize the device correctly until this pin is released.

3

GND

Ground Reference.

4

A0

Programmable Address for Multiple Package Decoding. The address pin can be updated on-the-fly.

5

SCL

Serial Clock Line.

6

SDA

Serial Data Input/Output.

7

Reference Input/Output. In the AD5693R-2, this is a reference output pin by default. It is recommended to use a

10 nF decoupling capacitor for the internal reference.

8

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

EPAD

Exposed Pad. Connect the exposed pad to GND.