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Data Sheet

AD5697R

Rev. B | Page 21 of 27

POWER-DOWN OPERATION

The AD5697R contains three separate power-down modes.

Command 0100 is designated for the power-down function (see

Table 7). These power-down modes are software programmable

by setting eight bits, Bit DB7 to Bit DB0, in the shift register. There

are two bits associated with each DAC channel. Table 10 shows

how the state of the two bits corresponds to the mode of operation

of the device.

Table 10. Modes of Operation

Operating Mode

PDx1

PDx0

Normal Operation

Power-Down Modes

1 kΩ to GND

100 kΩ to GND

Three-State

Either or both DACs (DAC A and DAC B) can be powered down

to the selected mode by setting the corresponding bits. See Table 11

for the contents of the input shift register during the power-down/

power-up operation.

When both Bit PDx1 and Bit PDx0 (where x is the channel

selected) in the input shift register are set to 0, the part works

normally with its normal power consumption of 4 mA at 5 V.

However, for the three power-down modes, the supply current

falls to 4 µA at 5 V. Not only does the supply current fall, but the

output stage is also internally switched from the output of the

amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode. There are three different power-

down options. The output is connected internally to GND through

either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited

(three-state). The output stage is illustrated in Figure 45.

Figure 45. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are shut down when the power-down

mode is activated. However, the contents of the DAC register

are unaffected when in power-down. The DAC register can be

updated while the device is in power-down mode. The time

required to exit power-down is typically 4.5 µs for VDD = 5 V.

To reduce the current consumption further, the on-chip reference

can be powered off. See the Internal Reference Setup section.

Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation1

DB23

(MSB)

DB22

DB21

DB20

DB19 to DB16

DB15 to DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

(LSB)

PDB1

PDB0

PDA1

PDA0

Command bits (C3 to C0)

Address bits, don’t care

Power-down,

select DAC B

Power-down,

select DAC A

X = don’t care.

RESISTOR

NETWORK

VOUTX

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

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