AD9783BCPZ datasheet(4/32 Pages) AD

4 / 32 page

AD9780/AD9781/AD9783

Data Sheet

Rev. C | Page 4 of 32

DIGITAL SPECIFICATIONS

TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless

otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

DAC CLOCK INPUT (CLKP, CLKN)

Differential Peak-to-Peak Voltage (CLKP − CLKN)

400

800

1600

Common-Mode Voltage

300

400

500

Maximum Clock Rate

500

MSPS

DAC CLOCK TO ANALOG OUTPUT DATA LATENCY

Cycles

SERIAL PERIPHERAL INTERFACE (CMOS INTERFACE)

Maximum Clock Rate (SCLK)

MHz

Minimum Pulse Width High

12.5

Minimum Pulse Width Low

12.5

Setup Time, SDI to SCLK (tDS)

2.0

Hold Time , SDI to to SCLK (tDH)

0.2

Data Valid ,SDO to SCLK, (tDV)

2.3

Setup time, CSB to SCLK (tDCSB)

1.4

SERIAL PERIPHERAL INTERFACE LOGIC LEVELS

Input Logic High

2.0

Input Logic Low

0.8

DIGITAL INPUT DATA (LVDS INTERFACE)

Input Voltage Range, VIA or VIB

800

1600

Input Differential Threshold, VIDTH

−100

+100

Input Differential Hysteresis, VIDTHH to VIDTHL

Input Differential Input Impedance, RIN

120

Ω

Maximum LVDS Input Rate (per DAC)

500

MSPS

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